module scheduler #(
  parameter NUM_CORES = 4
)(
  input  wire         clk,
  input  wire         rst_n,
  input  wire [31:0]  layer_config,
  output reg  [3:0]   core_active
);

  typedef enum {
    IDLE,
    LOAD_WEIGHTS,
    DATA_PROCESS,
    STORE_RESULTS
  } state_t;

  state_t current_state;
  
  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      current_state <= IDLE;
      core_active <= 0;
    end else begin
      case (current_state)
        IDLE: 
          if (layer_config[31]) begin
            current_state <= LOAD_WEIGHTS;
            core_active <= 4'b0001;
          end
          
        LOAD_WEIGHTS:
          if (load_complete) begin
            current_state <= DATA_PROCESS;
            core_active <= 4'b1111; // 激活所有核心
          end
          
        DATA_PROCESS:
          if (processing_done) 
            current_state <= STORE_RESULTS;
          
        STORE_RESULTS:
          if (store_done)
            current_state <= IDLE;
      endcase
    end
  end
  
  // 流水线计数器
  reg [7:0] cycle_count;
  always @(posedge clk) begin
    if (current_state == DATA_PROCESS)
      cycle_count <= cycle_count + 1;
    else
      cycle_count <= 0;
  end
endmodule